1. Field of the Invention
The present invention relates to semiconductor fabrication processes. More particularly, the present invention relates to methods for fabricating antifuse devices as a part of a CMOS integrated circuit fabrication process.
2. The Prior Art
Numerous processes for fabrication of antifuses are known in the prior art. Some of these processes may be easily integrated into already existing integrated circuit fabrication processes. Some antifuse elements incorporate a dielectric antifuse material which contains a nitride such as silicon nitride, either as a single layer, or as a part of a multilayer dielectric such as that described in U.S. Pat. Nos. 4,823,181 and 4,899,205. Such structures exhibit excellent leakage and reliability characteristics, and are thus preferred for certain applications.
Major thermal cycles associated with an antifuse fabrication process include oxidation of silicon nitride, drive in of arsenic dopant into polysilicon and oxidation of the polysilicon. While these thermal cycles are necessary for antifuse fabrication, they adversely impact the performance of transistors which are fabricated on the same integrated circuit as the antifuse. Such transistors include CMOS low voltage and high voltage active transistors, and in particular, field isolation transistors which separate the antifuses from each other.
The problem with the field transistor next to the antifuse is that when the thermal cycle is too long, this field transistor will become leaky. The degradation is introduced during antifuse processing, when an oxide-nitride-oxide antifuse material layer is formed not just in the antifuse region but also on top of the field oxide. After deposition and etching of polysilicon gate oxide, this nitride layer remains in the field oxide region under the polysilicon and becomes part of the field isolation transistor. Thermal cycle processes after nitride is formed will move nitrogen from the ONO nitride layer on top of the field oxide to the oxide/silicon interface. This creates positive traps, lowers the field transistor threshold, increases field transistor leakage, and eventually leads to poor isolation performance. As a result, during antifuse programming, this leakage will cause the antifuse adjacent to the desired antifuse to become programmed thus creating accidentally programmed antifuses. During normal operation, this leakage will contribute to the increase in standby leakage current.
In advanced CMOS or sub micron CMOS processes where the thermal budget after CMOS transistors are formed is very small, the long thermal budget associated with fabrication of the antifuses makes it unattractive for the antifuses to be processed after the CMOS transistors. One way to solve this problem from process viewpoint is to place the antifuse fabrication process before the transistor fabrication process. This eliminates exposing the transistors to the antifuse fabrication thermal cycles. However, the field isolation transistors which separate the antifuses from each other still suffer from the long thermal cycles and the added degradation associated with the thermal cycles. This happens because the top electrode of the antifuse forms the gate of the field transistors.
Circuits which help to alleviate this field isolation transistor problem are disclosed in U.S. Pat. No. 5,130,777. These circuits require additional layout area on the integrated circuit die. Sometimes the addition of these circuits adversely affects the flexibility of the antifuse programming algorithm and limits the optimization of the antifuse performance. Each thermal cycle is important. Therefore, the field transistor leakage should be reduced with processing step considerations. While it is necessary to reduce thermal cycles, it has to be kept in mind that oxide thickness on top of the nitride layer is very important in preventing antifuse leakage and improving antifuse manufacturing margin, especially in a plasma processing environment. In addition, the drive-in cycle for the arsenic dopant into the polysilicon is also important to ensure that arsenic is present close to the ONO interface to create a low resistance programmed antifuse.
The present invention is intended to solve this field isolation transistor problem from a process viewpoint. In addition, considerations are made to assure manufacturability and reliability of the antifuse. The present invention provides methods for forming antifuses which can maintain antifuse reliability while minimizing effects of antifuse process on field transistor performance.